The present invention relates to semiconductor devices and, more particularly, to static random access memories. It is a major objective of the present invention to enhance the speed of such memories.
Modern integrated circuit technology is dedicated in large part to making smaller and faster devices. Because of the large numbers required for most applications, integrated circuit memories play a significant role in determining the operational speed available in a system. A system's speed can be limited by the time required for accessing information from memory. Dynamic random access memories (DRAMs) are widely used because of their high levels of integration and relatively low cost; DRAMS, however, require refresh cycles which limit memory access speeds. Static random access memories (SRAMs) require no refreshing, and thus provide for faster memories, albeit at greater cost and lower levels of integration. Accordingly, SRAMS are a memory of choice in application requiring fast access times, for example, memory caches. However, these applications frequently call for even faster access times than are provided by available SRAMs.
A typical SRAM includes multiple memory cells. Each memory cell is a four or six-transistor device capable of storing a logic high or a logic low. When a given cell is selected it can be read from or written to, depending on the voltages applied to its outputs. Typically, an SRAM memory cell has complementary outputs. A sense amplifier is typically used to detect the sense of the differential between the complementary outputs to read the contents of a memory cell. A single sense amplifier can be connected to several memory cells. Select lines are used to enable at most one cell for each sense amplifier at any given time. In a typical memory configuration, a row select line carries the select signal that differentiates cells tied to a given sense amplifier.
There are two transition constraints which limit the speed with which SRAMs can be read. In the first place, there is a delay required for a bit-line signal to develop after a memory cell is addressed. In the second place, additional time is required for the bit lines to stabilize once a memory cell is deselected. In fact, some SRAMs include switches between complementary bit lines which can be closed after deselection to facilitate bit-line recovery and decrease the wait require for addressing another cell sharing the same bit lines. The disadvantage of this approach is that there is a delay between successive operations associated with the time required to turn the switch on to wait for stabilization, and then to turn the switch off.
What is needed is a faster method of stabilizing bit lines after cell deselection. Preferably, the method would also improve signal development time after cell selection to provide an overall improvement in cell access speeds.